SSD_DISP Panel Lighting Reference
1. Basic Introduction¶
1.1. Overview¶
This document mainly explains the configuration and use related to the panel lighting.
1.2. Chip related specifications¶
| Specifications Chip |
TTL | MIPI | SPI | SRGB | HDMI |
|---|---|---|---|---|---|
| 201/202 | Supported | Supported | Supported | ||
| 203 | not supported | not supported | supported | not supported | supported |
1.3. Keyword Description¶
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TTL/MIPI/SRGB (SSD20X does not support SRGB)
These are the LCD Panel interface.
The TTL interface signal type is TTL level, the content of the signal is RGB565 or RGB666 or RGB888, horizontal and vertical synchronization (HSYNC/VSYNC), clock (CLK) and data valid signal (DE).
The MIPI interface signal type is LVDS signal, and the content of the signal is video stream data and control instructions.
The SRGB interface divides the RGB data of one pixel into three transmissions to the panel.
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HDMI
High Definition Multimedia Interface is a fully digital video and sound transmission interface that can transmit uncompressed audio and video signals.
2. TTL Panel Lighting Introduction¶
2.1. Specifications¶
| Specifications Chip |
Maximum Resolution | Signal Format |
|---|---|---|
| 201/202 | 1280x720 60fps | RGB565/RGB666/RGB888 |
| 203 | Not supported | Not supported |
2.2. Basic Concepts¶
Parallel RGB Interface includes DE mode and HV mode. When DE mode is enabled, VSYNC, HSYNC, DOTCLK, DE, D[0-23] pins are used. When HV mode is enabled, VSYNC , HSYNC, DOTCLK, D[0-23] are used. Now the program uses DE mode by default, please configure relevant parameters according to DE mode.
The pins need to be initialized by some panel driver IC, which is actually the setting of their internal register, and they are usually communicating through the SPI or IIC interface. The cmd and data required for initialization are generally provided by the panel factory, and the data format needs to refer to the panel datasheet when sending.
Panels using Parallel RGB Interface require HSYNC, VSYNC, and DOTCLK as synchronization signals, and RGB data is only valid in a specific interval of timing.
The blanking interval in the line and field signals is an invisible area. Only the RGB data in the active interval will be finally displayed. Different panel Driver ICs have different requirements for the blanking interval.
In line signal:
Htotal = HSYNC + HBP + HFP + H Active
In field signal:
Vtotal = VSYNC + VBP + VFP + V Active
Finally calculate the pixel clock frequency:
Pixel CLK = Htotal * Vtotal * fps
The configuration related to the timing in the Panel parameters is mainly to adjust HSYNC, HBP, HFP in the line signal and VSYNC, VBP, VFP in the field signal. The length requirements of each part of the blanking interval will be provided in the panel spec.
The blanking interval is an adjustable range, and the final calculated pixel clk is also within a range.
The main control chip generally has a clock frequency limit, so when lighting a new panel, the pixel clk of the panel should be calculated first. If the key panel meets the requirements of the pixel clock frequency, it can generally be lighted.
Parallel RGB Interface Timing:
2.3. Panel Lighting Flow¶
2.4. Hardware related¶
2.4.1. View schematic¶
Take the schematic diagram of SSD202 demo board as an example.
Check the following schematic diagram to know the RGB888 data format and the corresponding Pins of CLK/HSYNC/VSYNC/DE:
Check the following schematic diagram to know the PWM (LCD_BL_PWM) and panel power enable (PNL_PWRCTL) required to control the timing sequence:
The corresponding pins on the chip side are as follows:
2.4.2. Corresponding to Padmux¶
Check the SSD202 HW CheckList to find the padmux corresponding to the pin, as follows:
2.5. Software related¶
2.5.1. Configuring padmux¶
It can be seen from the above that the panel uses ttl28_mode_1
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User space configuration Find the *padmux.dts configuration corresponding to the project as follows:
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Padmux configuration under Uboot
The RGB888/RGB666/RGB565 supported by TTL has been automatically switched to the corresponding Mode under Uboot according to the Lane num of the Panel parameter. Users can use it directly without paying attention (if the pin Mode is inconsistent, please consult the corresponding FAE for modification)
2.5.2. Configure Panel parameters¶
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Added Panel parameters
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SSD20X configures the Panel parameters in the form of a header file, first find a Panel parameter file with the public version Demo, here is an example of the public version TTL Panel reference SAT070CP50_1024x600.h (the header file is easy to see in the public version of each display Demo)
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Confirm the Panel specification and find the corresponding Timing specification, such as:
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Refer to the following Panel parameter descriptions, fill in the parameters corresponding to the Panel specifications into the header file, and then click the Panel to include the corresponding header file.
Parameters Description m_pPanelName panel name m_bPanelDither 1:enable Dither 0:disable Dither m_ePanelLinkType Interface type TTL :0 MIPI_DSI :10 m_bPanelInvDCLK Pixel clk polarity inversion m_bPanelInvDE DE polarity inversion m_bPanelInvHSync Hsync polarity inversion m_bPanelInvVSync Vsync polarity inversion m_wPanelHSyncWidth Pulse width of horizontal sync signal m_wPanelHSyncBackPorch HSync Back Porch m_wPanelVSyncWidth VSync signal pulse width m_wPanelVBackPorch VBackPorch m_wPanelHStart m_wPanelHSyncWidth+m_wPanelHSyncBackPorch m_wPanelVStart m_wPanelVSyncWidth+ m_wPanelVBackPorch m_wPanelWidth Number of valid pixels in a row m_wPanelHeight field valid number of lines m_wPanelHTotal m_wPanelWidth+m_wPanelHSyncWidth+m_wPanelHSyncBackPorch+HsyncFrontPorch m_wPanelVTotal m_wPanelHeight+m_wPanelVSyncWidth+ m_wPanelVBackPorch+VsyncFrontPorch m_wPanelDCLK m_wPanelHTotal m_wPanelVTotal fps (IP uses clk internally) m_wSpreadSpectrumFreq Clock spread amplitude modulation (see attachment: Spread Spectrum Calculation v2.xlsx) m_wSpreadSpectrumRatio Clock spread frequency modulation (see attachment: Spread Spectrum Calculation v2.xlsx) m_eOutputFormatBitMode 10BIT :0 //No use 6BIT :1 //RGB666 8BIT :2 //RGB888 565BIT :3 //RGB565 m_ucPanelSwapChnR Swap Channel R 0:default 1:select R 2:select G 3:select B m_ucPanelSwapChnG Swap Channel G 0:default 1:select R 2:select G 3:select B m_ucPanelSwapChnB Swap Channel B 0:default 1:select R 2:select G 3:select B m_ucPanelSwapRgbML Swap Rgb MSB/LSB 0:disable M/L swap 1:enable M/L swap If it is a mipi panel, you also need to configure the mipi dsi (corresponding to the MIPI point Panel in Chapter 3). The MIPI DSI parameters are described as follows: | Parameters | Description | | ------------- | ----------------------------------- ------------------------- | | m_wHsTrail | Default: 5 | | m_wHsPrpr | Default: 3 | | m_wHsZero | Default: 5 | | m_wClkHsPrpr | Default: 10 | | m_wClkHsExit | Default: 14 | | m_wClkTrail | Default: 3 | | m_wClkZero | Default: 12 | | m_wClkHsPost | Default: 10 | | m_wDaHsExit | Default: 5 | | m_wContDet | Default:0 | | m_wLpx | Default:16 | | m_wTaGet | Default:26 | | m_wTaSure | Default:24 | | m_wTaGo | Default:50 | | m_wHactive | Follow Panel parameter setting | | m_wHpw | Follow Panel parameter setting | | m_wHbp | Follow Panel parameter setting | | m_wHfp | Follow Panel parameter setting | | m_wVactive | Follow Panel parameter setting | | m_wVpw | Follow Panel parameter setting | | m_wVbp | Follow Panel parameter setting | | m_wVfp | Follow Panel parameter setting | | m_wBllp | 0 | | m_wFps | Default:60 | | m_eLaneNum | one lane :1 two lane :2 three lane :3 four lane :4 | | m_eFormat | RGB565 :0 RGB666 :1 LOOSELY_RGB666 :2 RGB888 :3 | | m_eCtrlMode | CMD_MODE :0 SYNC_PULSE :1 SYNC_EVENT :2 BURST_MODE :3 | | m_ucClkLane | Clk lane selection(default:2) 0:select chn0 1:select chn1 2:select chn2 3:select chn3 4:select chn4 | | m_ucDataLane0 | data lane0 selection(default:4) 0:select chn0 1:select chn1 2:select chn2 3:select chn3 4:select chn4 | | m_ucDataLane1 | data lane1 selection(default:3) 0:select chn0 1:select chn1 2:select chn2 3:select chn3 4:select chn4 | | m_ucDataLane2 | data lane2 selection(default:1) 0:select chn0 1:select chn1 2:select chn2 3:select chn3 4:select chn4 | | m_ucDataLane3 | data lane3 selection(default:0) 0:select chn0 1:select chn1 2:select chn2 3:select chn3 4:select chn4 | | m_pCmdBuff | Mipi panel cmd m_pCmdBuff= { Cmd, parameter cnt, parameter0, parameter1, … , Cmd, parameter cnt, parameter0, parameter1, … , Cmd, parameter cnt, parameter0, parameter1, … , ……… } | | m_ucPolCh0 | Chn0 polarity 0: default 1: positive 2: negative | | m_ucPolCh1 | Chn1 polarity 0: default 1: positive 2: negative | | m_ucPolCh2 | Chn2 polarity 0: default 1: positive 2: negative | | m_ucPolCh3 | Chn3 polarity 0: default 1: positive 2: negative | | m_ucPolCh4 | Chn4 polarity 0: default 1: positive 2: negative | -
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code example
1. #include "SAT070CP50_1024x600.h" 2. 3. int sstar_disp_init(MI_DISP_PubAttr_t *pstDispPubAttr, int disp_port_num) 4. { 5. MI_PANEL_LinkType_e eLinkType; 6. 7. if (pstDispPubAttr->eIntfType == E_MI_DISP_INTF_LCD) 8. { 9. pstDispPubAttr->stSyncInfo.u16Vact = stPanelParam.u16Height; 10. pstDispPubAttr->stSyncInfo.u16Vbb = stPanelParam.u16VSyncBackPorch; 11. pstDispPubAttr->stSyncInfo.u16Vfb = stPanelParam.u16VTotal - (stPanelParam.u16VSyncWidth + 12. stPanelParam.u16Height + stPanelParam.u16VSyncBackPorch); 13. pstDispPubAttr->stSyncInfo.u16Hact = stPanelParam.u16Width; 14. pstDispPubAttr->stSyncInfo.u16Hbb = stPanelParam.u16HSyncBackPorch; 15. pstDispPubAttr->stSyncInfo.u16Hfb = stPanelParam.u16HTotal - (stPanelParam.u16HSyncWidth + 16. stPanelParam.u16Width + stPanelParam.u16HSyncBackPorch); 17. pstDispPubAttr->stSyncInfo.u16Bvact = 0; 18. pstDispPubAttr->stSyncInfo.u16Bvbb = 0; 19. pstDispPubAttr->stSyncInfo.u16Bvfb = 0; 20. pstDispPubAttr->stSyncInfo.u16Hpw = stPanelParam.u16HSyncWidth; 21. pstDispPubAttr->stSyncInfo.u16Vpw = stPanelParam.u16VSyncWidth; 22. pstDispPubAttr->stSyncInfo.u32FrameRate = stPanelParam.u16DCLK * 1000000 / (stPanelParam.u16HTotal * stPanelParam.u16VTotal); 23. pstDispPubAttr->eIntfSync = E_MI_DISP_OUTPUT_USER; 24. pstDispPubAttr->eIntfType = E_MI_DISP_INTF_LCD; 25. eLinkType = stPanelParam.eLinkType; 26. 27. MI_DISP_SetPubAttr(0, pstDispPubAttr); 28. MI_DISP_Enable(0); 29. 30. MI_PANEL_Init(eLinkType); 31. MI_PANEL_SetPanelParam(&stPanelParam); 32. } 33. return 0; 34. }
2.6. Debug method¶
cat /proc/mi_modules/mi_panel/mi_panel0
3. MIPI Panel introduction¶
3.1. Specifications¶
| Specifications Chip |
MIPI |
|---|---|
| 201/201 | Support |
| 203 | Not support |
MIPI DSI Specifications:
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1-4 data lanes, 1 clock lane
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Level
LP: 0~12V
HS: 100~300mV
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HS: 80Mbps ~ 1.5Gbps/lane
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Pixel format
16 bpp (5,6,5 RGB) each pixel using two bytes
18 bpp (6,6,6 RGB) packed
18 bpp (6, 6, 6 RGB) loosely packed into three bytes
24 bpp (8, 8, 8 RGB), each pixel using three bytes
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video mode: BURST_MODE/SYNC_EVENT/SYNC_PULSE
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data/clk chn swap
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data/clk chn P/N swap
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data clk skew adjustment
3.2. Basic Concepts¶
MIPI DPHY timing chart:
Figure 3-1: Data lanes-Low Power Mode to/from High Speed Mode Timing
Figure 3-2: Clock lanes- High Speed Mode to/from Low Power Mode Timing
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Configure HS Timing Parameter
HS_TRAIL/HS_EXIT /HS_PRPR/HS_ZERO/CLK_PRPR/CLK_ZERO/CLK_POST/CLK_TRAIL
Timing specification THS-PREPARE + THS-zero 145ns+10*UI THS-PREPARE 40ns+4 UI ~ 85ns +6 UI THS-ZERO >60ns+4 UI ~105ns+6 UI UI represents the time interval, equal to the duration of any HS state on the clock channel.
UI calculation method:
H_Total = HACT+HPW+HBP+HFP V_Total = VACT+VPW+VBP+VFP BitsPerPixel=24(RGB888)/18(RGB666)/16(RGB565) Bitrate = (H_Total)*(V_Total)*FPS* BitsPerPixel/lane number UI = 1/Bitrate
Figure 3-3 DSI clock channel timing
If Bitrate = 750Mps, UI = 1/Bitrate = 1.333ns, then the calculation result of HS timing parameter is:
Timing specification Absolute time DA_HS_PREP value (Absolute time/(8*UI)) THS-PREPARE + THS-zero 145ns+10*UI > 158.33 ns > 15 THS-PREPARE 40ns+4*UI ~ 85ns +6*UI 45.32 ~ 92.98 ns 5 ~ 8 THS-zero >60ns+4*UI ~105ns+6*UI > 112.98~ 65.32 ns 10 ~ 7 -
Configure LP Timing Parameter
CONT_DET/LPX/TA_GET/TA_SURE/TA_GO
It is recommended to use the provided default values for low power parameters
DCS (Display Command Set) protocol: DCS is a standardized command set for display modules in command mode.
DSI (Display Serial Interface) is divided into four layers, corresponding to D-PHY, DSI, DCS specifications, and the layered structure diagram is as above:
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PHY defines the transmission medium, input/output circuits and clocking and signaling mechanisms.
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Lane Management layer: send and collect data flow to each lane.
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Low Level Protocol layer: defines how to frame and parse, and error detection.
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Application layer: Describes high-level encoding and parsing data streams.
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3.3. Hardware related¶
3.3.1. View schematic¶
Demo Board schematic:
As shown in the figure above, the corresponding pins inside the chip by default are:
Lane0 corresponds to PAD_TTL6/7 → E_MI_PNL_CH_SWAP_0 (the corresponding enumeration value is 0)
Lane1 corresponds to PAD_TTL8/9 → E_MI_PNL_CH_SWAP_1 (the corresponding enumeration value is 1)
Lane2 corresponds to PAD_TTL12/13 → E_MI_PNL_CH_SWAP_3 (the corresponding enumeration value is 3)
Lane3 corresponds to PAD_TTL14/15 → E_MI_PNL_CH_SWAP_4 (the corresponding enumeration value is 4)
Clk corresponds to PAD_TTL10/11 → E_MI_PNL_CH_SWAP_2 (the corresponding enumeration value is 2)
The enumeration values here are software-defined, refer to the MIPI Swap field configuration described next
3.3.2. Corresponding to padmux¶
Confirm the hardware design pin connection
The following picture is the recommended mipi pin, PAD TTL6 – PAD TTL15 (MIPI Mode 1)
3.4. Software related¶
3.4.1. Configuring padmux¶
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User space configuration Find the *padmux.dts configuration corresponding to the project corresponding to MIPI MODE
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Padmux configuration under Uboot
MIPI is commonly used 2Lane and 4Lane. Under Uboot, it has been automatically switched to the corresponding Mode according to the Lane num of the Panel parameter. Users can use it directly without paying attention.
3.4.2. Configure Panel parameters¶
Confirm panel specifications:
HTotal = u16Width + u16HSyncWidth + u16HSyncBackPorch + HSyncFrontPorch
VTotal = u16Heigth + u16VSyncWidth + u16VSyncBackPorch + HVyncFrontPorch
DCLK = HTotal * VTotal * FPS
3.4.3. Code Examples¶
The configuration of MIPI Panel parameters will be slightly different than that of TTL, mainly focus on two structures, pay attention to the parameter settings:
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Configure MI_PANEL_MipiDsiConfig_t (TTL does not need to be concerned)
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Part 2 is mainly to set the H/V related parameters listed in the Panel specification, and fill in the connection options one by one according to the TTL method.
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Part3 is mainly the initialization cmd of the Panel. This part of the cmd is customized by each panel manufacturer with reference to the DSC standard, so the cmd is generally provided by the original chip manufacturer of the Panel.
1. static MI_U8 cmd_buf[] = 2. { 3. cmd1, data_num, data[0],data[1],...,data[num-1], 4. ..., 5. cmdN, data_num, data[0],data[1],...,data[num-1], 6. FLAG_END_OF_TABLE, FLAG_END_OF_TABLE, //Terminator 7. } -
Part4 is to set the P/N polarity of each Lane to be reversed. Refer to the connection between the hardware and the Panel to confirm whether it needs to be reversed.
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Part 1 is mainly for the timing requirements during the transmission process. In this part, we have prepared a general Excel table (attachment: [mipi related parameter calculation v2.xlsx] (mymedia/disp/mipi related parameter calculation v2.xlsx)). As long as you enter the HTotal/VTotal corresponding to the Panel, it will be automatically generated. The example is as follows:
The red box part is the scream that is automatically generated according to the formula, and you can fine-tune the corresponding and fill in the software Panel parameters within the range.
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MI_PANEL_ParamConfig_t: mainly depends on the MIPI Swap configuration field (TTL does not need to be concerned)
1. typedef enum 2. { 3. E_MI_PNL_CH_SWAP_0, 4. E_MI_PNL_CH_SWAP_1, 5. E_MI_PNL_CH_SWAP_2, 6. E_MI_PNL_CH_SWAP_3, 7. E_MI_PNL_CH_SWAP_4, 8. }MI_PANEL_ChannelSwapType_e; 9. 10. typedef struct 11. { 12. ... 13. ... 14. MI_PANEL_ChannelSwapType_e eCh0; //--> CLK field 15. MI_PANEL_ChannelSwapType_e eCh1; //--> Lane3 field 16. MI_PANEL_ChannelSwapType_e eCh2; //--> Lane2 field 17. MI_PANEL_ChannelSwapType_e eCh3; //--> Lane1 field 18. MI_PANEL_ChannelSwapType_e eCh4; //--> Lane0 field 19. }MI_PANEL_ParamConfig_t;You need to refer to the actual hardware connection configuration. Considering that the external device Lane To Lane does not Swap, the parameters should be configured as follows:
1. typedef struct 2. { 3. ... 4. ... 5. MI_PANEL_ChannelSwapType_e eCh0; //--> CLK field -- E_MI_PNL_CH_SWAP_2 6. MI_PANEL_ChannelSwapType_e eCh1; //--> Lane3 field -- E_MI_PNL_CH_SWAP_4 7. MI_PANEL_ChannelSwapType_e eCh2; //--> Lane2 field -- E_MI_PNL_CH_SWAP_3 8. MI_PANEL_ChannelSwapType_e eCh3; //--> Lane1 field -- E_MI_PNL_CH_SWAP_1 9. MI_PANEL_ChannelSwapType_e eCh4; //--> Lane0 field -- E_MI_PNL_CH_SWAP_0 10. }MI_PANEL_ParamConfig_t;That is 2, 4, 3, 1, 0
Panel Lighting sample:
35. int sstar_disp_init(MI_DISP_PubAttr_t *pstDispPubAttr, int disp_port_num)
36. {
37. MI_PANEL_LinkType_e eLinkType;
38.
39. if (pstDispPubAttr->eIntfType == E_MI_DISP_INTF_LCD)
40. {
41. pstDispPubAttr->stSyncInfo.u16Vact = stPanelParam.u16Height;
42. pstDispPubAttr->stSyncInfo.u16Vbb = stPanelParam.u16VSyncBackPorch;
43. pstDispPubAttr->stSyncInfo.u16Vfb = stPanelParam.u16VTotal - (stPanelParam.u16VSyncWidth +
44. stPanelParam.u16Height + stPanelParam.u16VSyncBackPorch);
45. pstDispPubAttr->stSyncInfo.u16Hact = stPanelParam.u16Width;
46. pstDispPubAttr->stSyncInfo.u16Hbb = stPanelParam.u16HSyncBackPorch;
47. pstDispPubAttr->stSyncInfo.u16Hfb = stPanelParam.u16HTotal - (stPanelParam.u16HSyncWidth +
48. stPanelParam.u16Width + stPanelParam.u16HSyncBackPorch);
49. pstDispPubAttr->stSyncInfo.u16Bvact = 0;
50. pstDispPubAttr->stSyncInfo.u16Bvbb = 0;
51. pstDispPubAttr->stSyncInfo.u16Bvfb = 0;
52. pstDispPubAttr->stSyncInfo.u16Hpw = stPanelParam.u16HSyncWidth;
53. pstDispPubAttr->stSyncInfo.u16Vpw = stPanelParam.u16VSyncWidth;
54. pstDispPubAttr->stSyncInfo.u32FrameRate = stPanelParam.u16DCLK * 1000000 / (stPanelParam.u16HTotal * stPanelParam.u16VTotal);
55. pstDispPubAttr->eIntfSync = E_MI_DISP_OUTPUT_USER;
56. pstDispPubAttr->eIntfType = E_MI_DISP_INTF_LCD;
57. eLinkType = stPanelParam.eLinkType;
58.
59. MI_DISP_SetPubAttr(0, pstDispPubAttr);
60. MI_DISP_Enable(0);
61.
62. MI_PANEL_Init(eLinkType);
63. MI_PANEL_SetPanelParam(&stPanelParam);
64. if(eLinkType == E_MI_PNL_LINK_MIPI_DSI)
65. {
66. MI_PANEL_SetMipiDsiConfig(&stMipiDsiConfig);
67. }
68.
69. }
70. return 0;
71. }
3.5. Debug Method¶
cat /proc/mi_modules/mi_panel/mi_panel0
4. HDMI Output¶
4.1. Specifications¶
HDMI, the full name is High Definition Multimedia Interface.
HDMI 1.4b transmitter up to 4k2k@30
Regular resolution:
DACOUT_480P_60 DACOUT_576P_50 DACOUT_720P_50 DACOUT_720P_60 DACOUT_1024X768P_60 DACOUT_1080P_24 DACOUT_1080P_25 DACOUT_1080P_30 DACOUT_1080P_50 DACOUT_1080P_60 DACOUT_1920X1200P_60 DACOUT_1280X1024P_60 DACOUT_1280X800P_60 DACOUT_1366X768P_60 DACOUT_1440X900P_60 DACOUT_1600X1200P_60 DACOUT_1680X1050P_60 DACOUT_4K2KP_30
4.2. Basic Concepts¶
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Standard HDMI connector
Pin Signal 1 TMDS Data2+ 2 TMDS Data2 Shield 3 TMDS Data2 4 TMDS Data1+ 5 TMDS Data1 Shield 6 TMDS Data1– 7 TMDS Data0+ 8 TMDS Data0 Shield 9 TMDS Data0– 10 TMDS Clock+ 11 TMDS Clock Shield 12 TMDS Clock– 13 CEC 14 Reserved (N.C. on device) 15 SCL 16 SDA 17 DDC/CEC Ground 18 + 5V 19 Hot Plug Detect -
DDC channel
The full name of DDC is Display Data Channel
The transmitting end and the receiving end can use the DDC channel to know each other's transmission and receiving capabilities, but HDMI only needs to know the ability of the receiving end (display) in one direction
I²C signal using 100kHz clock frequency
The transfer data structure is VESA Enhanced EDID (V1.3)
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TMDS channel
Transmission of audio, video, and various auxiliary data
Signal encoding method: follow the DVI 1.0 specification. Single-link (Type A HDMI)
Video pixel bandwidth: The allowable amount of data per pixel is from 24 to 48 bits. Supports 1080p at 60 frames per second
Pixel encoding method: RGB 4:4:4, YCbCr 4:4:4; YCbCr 4:2:2
Audio sample rate: 32 kHz, 48 kHz
Audio channels: maximum 2 channels
Audio stream specification: PCM Audio/16BIT
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HPD
HPD (Hotplug) is a prelude signal sent by the sink device (Sink) to establish formal communication with the HDMI source device (Source). When the HPD signal level is high, it indicates that the sink device is ready, allowing the source device to access the sink device.
4.3. Panel tap process¶
The HDMI interface is a fixed interface, please refer to the following hardware and software configuration.
4.4. Hardware related¶
IC pin interface:
4.5. Software related¶
4.5.1. Dts config and pad mux config¶
hdmitx: hdmitx {
compatible = "sstar,hdmitx";
status = "ok";
i2c_id = <0>;
hpd_gpio = <89>;
i2c_sw = <1>;
i2c_sda_gpio = <88>;
i2c_scl_gpio = <87>;
clocks = <&CLK_hdmi>, <&CLK_disp_432>, <&CLK_disp_216>;
clock-names = "CLK_hdmi", "CLK_disp_432", "CLK_disp_216";
//Reg = <0x1F224000 0x200>;
};
The pin of Gpio.h corresponds to the gpio port.
#define PAD_HDMITX_SCL 87 #define PAD_HDMITX_SDA 88 #define PAD_HDMITX_HPD 89
Which needs to be explained: it is reliable and compatible for iic communication. The swiic method is used by default. Among them, PAD_HDMITX_HPD is the hot-plug detection port by default.
4.5.2. Initialization and parameter setting¶
Hdmi related code:
/* Base Module Init */ stInitParam.pCallBackArgs = NULL; stInitParam.pfnHdmiEventCallback = Hdmi_callback_impl; ExecFunc(MI_HDMI_Init(&stInitParam), MI_SUCCESS); ExecFunc(MI_HDMI_Open(eHdmi), MI_SUCCESS); ExecFunc(MI_HDMI_SetAttr(eHdmi, &stAttr), MI_SUCCESS); ExecFunc(MI_HDMI_Start(eHdmi), MI_SUCCESS); //ExecFunc(MI_HDMI_SetAvMute(eHdmi, true), MI_SUCCESS);// first no audio ExecFunc(MI_HDMI_SetAvMute(eHdmi, false), MI_SUCCESS);
Display and hdmi interface:
memset(&stPubAttr, 0x00, sizeof(MI_DISP_PubAttr_t)); stPubAttr.u32BgColor = YUYV_BLACK; stPubAttr.eIntfType = E_MI_DISP_INTF_HDMI; stPubAttr.eIntfSync = eOutputTiming; /* Set Disp Pub */ ExecFunc(MI_DISP_SetPubAttr(DispDev, &stPubAttr), MI_SUCCESS); ExecFunc(MI_DISP_Enable(DispDev), MI_SUCCESS);
Hdmi parameters:
MI_HDMI_Attr_t stAttr; stAttr.stEnInfoFrame.bEnableAudInfoFrame = true; stAttr.stEnInfoFrame.bEnableAviInfoFrame = true; stAttr.stEnInfoFrame.bEnableSpdInfoFrame = true; stAttr.stAudioAttr.bEnableAudio = true; stAttr.stAudioAttr.bIsMultiChannel = 0; stAttr.stAudioAttr.eBitDepth = E_MI_HDMI_BIT_DEPTH_16; stAttr.stAudioAttr.eCodeType = E_MI_HDMI_ACODE_PCM; stAttr.stAudioAttr.eSampleRate = E_MI_HDMI_AUDIO_SAMPLERATE_48K; stAttr.stVideoAttr.bEnableVideo = true; stAttr.stVideoAttr.eColorType = E_MI_HDMI_COLOR_TYPE_RGB444;//default color type stAttr.stVideoAttr.eDeepColorMode = E_MI_HDMI_DEEP_COLOR_MAX; stAttr.stVideoAttr.eOutputMode = E_MI_HDMI_OUTPUT_MODE_HDMI; stAttr.stVideoAttr.eTimingType = E_MI_HDMI_TIMING_1080_60P;//1080P60 -> 720P60 s32ret = MI_HDMI_SetAttr(eHdmi, &stAttr);
5. SPI Panel Lighting Introduction¶
5.1. Specifications¶
| Specifications Chip |
SPI |
|---|---|
| 201/202 | Support |
| 203 | Support |
5.2. Basic Concepts¶
SPI: Serial Peripheral Interface.
Use the spi interface to generally point to a smaller resolution lcd.
5.3. Panel Lighting Flow¶
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Configure the SPI PIN according to the schematic diagram. Query the CheckList table and change the dts file to configure the PIN_MUX of the corresponding pin.
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Enable SPI driver in Kernel
Enable the following options under menuconfig:
> Device Drivers > Sstar Soc platform drivers > Sstar MSPI driver -
According to the initialization command under the data sheet. The initialization command is generally provided by the panel factory, or you can view the panel specification and configure it yourself.
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Write the image data and display the Panel. Some Panels come with an internal test part, which can be enabled for output through commands.
5.4. Hardware related¶
5.4.1. Viewing the schematic¶
Taking SPI as an example, a hardware engineer will query the HW CheckList table when drawing a schematic diagram, and select a set of free pins that can be used as SPI interface pins. We choose PAD_GPIO8-PAD_GPIO11, and PADMUX choose SPI0_MODE_5.
5.4.2 Corresponding padmux¶
5.5. Software related¶
5.5.1. Configure related padmux¶
In the case of PADMUX with known pins , we need to change the corresponding padmux.dtsi file in the kernel/arch/arm/boot/dts directory to ensure the correct PADMUX switching. Take SPI0_MODE_5 as an example:
5.5.2. Configure Panel Parameters¶
SPI does not have the Panel parameter configuration similar to our TTL, mainly according to the initialization command under the data sheet. The initialization command is generally provided by the panel factory, or you can view the panel specification and configure it yourself.
5.5.3. Code Examples¶
There are two development methods for SPI Panel:
a. Directly send the YUV/RGB data to the panel through SPI, this operation can refer to the SPI in the BSP to use the reference data to send (not repeated below)
b. The native framework of the kernel is connected to the spi through the bottom layer of fbtft. The user operation only needs to operate /dev/fb1 abstracted by fbtft. For details, please refer to chapter 5.6.
5.6. Fbtft development advice¶
For the spi panel, it is recommended to use the native architecture of the kernel to develop and use the TFT-LCD driver.
5.6.1. Spi panel driver configuration¶
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Open fbtft config in Kernel menuconfig, and compile the markup in the figure into a module
Note: Support for small TFT LCD display needs to be set to
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Dts add corresponding configuration
After compiling, install with the following command:
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Remove the original fbdev.ko and restart the platform
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Load the fbtft module after rebooting
insmod /config/modules/4.9.84/fbtft_device.ko busnum=1 name=admatec_b-berry28 cs=0 gpios="reset:21,dc:20" custom=1 speed=40000000 width=240 height=320 buswidth=8 mode=0 debug=7 dma=0
Note: name=admatec_b-berry28 should be consistent with the name of the driver fbtft_device_display displays[]. If the Speed parameter is too high, spi timeout may occur . You can try to reduce the speed for debugging.
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Load the corresponding TFT driver: insmod /config/modules/fb_st7796s.ko
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Changes related to panel settings
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Panel initialization
Fbtft-core.c:
fbtft_probe_common() -> fbtft_register_framebuffer() -> fbtftops.init_display()
The panel will be initialized with the following array initialization parameters:
Other settings are in fbtftops.set_var()/fbtftops.update_display()fbtftops.set_gamma()
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Refresh
The upper layer refreshes fb through ioctl(g_fbFd, FBIOPAN_DISPLAY, &vinfo)
Corresponding bottom layer:
fbtft_update_display() -> fbtftops.write_vmem() -> fbtft_write_vmem16_bus8() -> fbtftops.write -> fbtft_write_spi()
Note: Because the spi directly sends data to the panel, the data sent by RGB565 or RGB888 is different, so the data data sent by the upper layer to the driver needs to conform to the data format of the Panel. If the flythings used by the gui need to close the gfx module: export ZK_GFX_ENABLE=0
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5.7. Debug method¶
If the SPI Panel does not light up, you can check it from the following methods:
a. Is the padmux of the spi configured correctly? It can be confirmed by looking at the registers and measuring the waveform in hardware.
b. Whether the spi initialization command is correct, you can contact the Panel factory to confirm, and you can send the spi command to play the test pattern to test whether the hardware is connected.
6. Frequently Asked Questions¶
The backlight can be on, but there is no picture, please check the following problems:
a. Check whether the Panel parameters meet the panel spec requirements
b. Whether the data flow is normal and whether there is input buff input
c. Whether the relevant settings of DISP device/layer/input port are reasonable
d. Whether the panel init is successful, the TTL panel that needs SPI initialization can measure whether the SPI signal is normal and whether the initial cmd is correctly transmitted
e. Check whether the polarity of Hsync/Vsync/DE/Dclk meets the panel spec
f. MIPI panel check whether the line sequence of clk lane/data lane is consistent with the software setting
g. Check whether riu_r 0x101e 0xd has cut to the correct TTL mode(value:0x100)/MIPI mode(value:0x1000)