SSU_TIMER使用参考

REVISION HISTORY

Revision No.
Description
 Date
1.0
  • Initial release
    		•  11/03/2022

    1. 使用说明

    1.1. Enable Timer

    1. Enable Timer engine – set “TIMER_EN” to 1
    2. Trigger counter – set” TIMER_TRIG” to 1.
    3. Read timer from register “TIMER_CAP[31:0]”

    1.2. Set Divide and Maximum

    1. Set the “divide” value to “TIMER_DIVIDE[7:0] for timer counter frequency
    2. Set the “max” value to “TIMER_MAX[31:0]”.
    3. Enable timer
    4. If counter over the “TIMER_MAX[31:0]”, then “TIMER_HIT” will assert.

    2. REGISTER TABLE

    2.1. TIMER0 Register (Bank = 30)

    Index (Absolute) Mnemonic Bit Description
    10h (3020h) REG3020 7:0 Default : 0x00 Access : R/W
    - 7:2 Reserved.
    TIMER_TRIG 1 set: Enable timer counting one time (from 0 to max, then stop).
    clear: By reset itself OR set reg_timer_en.
    TIMER_EN 0 set: Enable timer counting rolled (from 0 to max, then rolled).
    clear: By reset itself OR set reg_timer_trig.
    10h (3021h) REG3021 7:0 Default : 0x00 Access : R/W
    - 7:1 Reserved.
    TIMER_INT_EN 0 set: Enable interrupt.
    clear: By reset itself.
    11h (3022h) REG3022 7:0 Default : 0x00 Access : RO
    - 7:1 Reserved.
    TIMER_HIT 0 assert: When counter enabled and matches reg_timer_max.
    deassert: By write 1 OR set reg_timer_en, reg_timer_once, reg_timer_max.
    12h (3024h) REG3024 7:0 Default : 0xFF Access : R/W
    TIMER_MAX[7:0] 7:0 Timer maximum value.
    12h (3025h) REG3025 7:0 Default : 0xFF Access : R/W
    TIMER_MAX[15:8] 7:0 See description of '3024h'.
    13h (3026h) REG3026 7:0 Default : 0xFF Access : R/W
    TIMER_MAX[23:16] 7:0 See description of '3024h'.
    13h (3027h) REG3027 7:0 Default : 0xFF Access : R/W
    TIMER_MAX[31:24] 7:0 See description of '3024h'.
    14h (3028h) REG3028 7:0 Default : 0x00 Access : RO
    TIMER_CAP[7:0] 7:0 Timer current value.
    Note: With non-32-bit-data system, please read from LSB.
    14h (3029h) REG3029 7:0 Default : 0x00 Access : RO
    TIMER_CAP[15:8] 7:0 See description of '3028h'.
    15h (302Ah) REG302A 7:0 Default : 0x00 Access : RO
    TIMER_CAP[23:16] 7:0 See description of '3028h'.
    15h (302Bh) REG302B 7:0 Default : 0x00 Access : RO
    TIMER_CAP[31:24] 7:0 See description of '3028h'.
    16h (302Ch) REG302C 7:0 Default : 0x00 Access : R/W
    TIMER_DIVIDE[7:0] 7:0 timer divide counter number
    8'b0000: timer counter = clk_xiu/1
    8'b0001: timer counter = clk_xiu/2
    8'b0010: timer counter = clk_xiu/3
    and so on

    2.2. TIMER1 Register (Bank = 30)

    Index (Absolute) Mnemonic Bit Description
    20h (3040h) REG3040 7:0 Default : 0x00 Access : R/W
    - 7:2 Reserved.
    TIMER_TRIG 1 set: Enable timer counting one time (from 0 to max, then stop).
    clear: By reset itself OR set reg_timer_en.
    TIMER_EN 0 set: Enable timer counting rolled (from 0 to max, then rolled).
    clear: By reset itself OR set reg_timer_trig.
    20h (3041h) REG3041 7:0 Default : 0x00 Access : R/W
    - 7:1 Reserved.
    TIMER_INT_EN 0 set: Enable interrupt.
    clear: By reset itself.
    21h (3042h) REG3042 7:0 Default : 0x00 Access : RO
    - 7:1 Reserved.
    TIMER_HIT 0 assert: When counter enabled and matches reg_timer_max.
    deassert: By write 1 OR set reg_timer_en, reg_timer_once, reg_timer_max.
    22h (3044h) REG3044 7:0 Default : 0xFF Access : R/W
    TIMER_MAX[7:0] 7:0 Timer maximum value.
    22h (3045h) REG3045 7:0 Default : 0xFF Access : R/W
    TIMER_MAX[15:8] 7:0 See description of '3044h'.
    23h (3046h) REG3046 7:0 Default : 0xFF Access : R/W
    TIMER_MAX[23:16] 7:0 See description of '3044h'.
    23h (3047h) REG3047 7:0 Default : 0xFF Access : R/W
    TIMER_MAX[31:24] 7:0 See description of '3044h'.
    24h (3048h) REG3048 7:0 Default : 0x00 Access : RO
    TIMER_CAP[7:0] 7:0 Timer current value.
    Note: With non-32-bit-data system, please read from LSB.
    24h (3049h) REG3049 7:0 Default : 0x00 Access : RO
    TIMER_CAP[15:8] 7:0 See description of '3048h'.
    25h (304Ah) REG304A 7:0 Default : 0x00 Access : RO
    TIMER_CAP[23:16] 7:0 See description of '3048h'.
    25h (304Bh) REG304B 7:0 Default : 0x00 Access : RO
    TIMER_CAP[31:24] 7:0 See description of '3048h'.
    26h (304Ch) REG304C 7:0 Default : 0x00
    TIMER_DIVIDE[7:0] 7:0 timer divide counter number
    8'b0000: timer counter = clk_xiu/1
    8'b0001: timer counter = clk_xiu/2
    8'b0010: timer counter = clk_xiu/3
    and so on

    2.3. TIMER2 Register (Bank = 30)

    Index (Absolute) Mnemonic Bit Description
    30h (3060h) REG3060 7:0 Default : 0x00 Access : R/W
    - 7:2 Reserved.
    TIMER_TRIG 1 set: Enable timer counting one time (from 0 to max, then stop).
    clear: By reset itself OR set reg_timer_en.
    TIMER_EN 0 set: Enable timer counting rolled (from 0 to max, then rolled).
    clear: By reset itself OR set reg_timer_trig.
    30h (3061h) REG3061 7:0 Default : 0x00 Access : R/W
    - 7:1 Reserved.
    TIMER_INT_EN 0 set: Enable interrupt.
    clear: By reset itself.
    31h (3062h) REG3062 7:0 Default : 0x00 Access : RO
    - 7:1 Reserved.
    TIMER_HIT 0 assert: When counter enabled and matches reg_timer_max.
    deassert: By write 1 OR set reg_timer_en, reg_timer_once, reg_timer_max.
    32h (3064h) REG3064 7:0 Default : 0xFF Access : R/W
    TIMER_MAX[7:0] 7:0 Timer maximum value.
    32h (3065h) REG3065 7:0 Default : 0xFF Access : R/W
    TIMER_MAX[15:8] 7:0 See description of '3064h'.
    33h (3066h) REG3066 7:0 Default : 0xFF Access : R/W
    TIMER_MAX[23:16] 7:0 See description of '3064h'.
    33h (3067h) REG3067 7:0 Default : 0xFF Access : R/W
    TIMER_MAX[31:24] 7:0 See description of '3064h'.
    34h (3068h) REG3068 7:0 Default : 0x00 Access : RO
    TIMER_CAP[7:0] 7:0 Timer current value.
    Note: With non-32-bit-data system, please read from LSB.
    34h (3069h) REG3069 7:0 Default : 0x00 Access : RO
    TIMER_CAP[15:8] 7:0 See description of '3068h'.
    35h (306Ah) REG306A 7:0 Default : 0x00 Access : RO
    TIMER_CAP[23:16] 7:0 See description of '3068h'.
    35h (306Bh) REG306B 7:0 Default : 0x00 Access : RO
    TIMER_CAP[31:24] 7:0 See description of '3068h'.
    36h (306Ch) REG306C 7:0 Default : 0x00
    TIMER_DIVIDE[7:0] 7:0 timer divide counter number
    8'b0000: timer counter = clk_xiu/1
    8'b0001: timer counter = clk_xiu/2
    8'b0010: timer counter = clk_xiu/3
    and so on

    2.4. TIMER3 Register (Bank = 30)

    Index (Absolute) Mnemonic Bit Description
    40h (3080h) REG3080 7:0 Default : 0x00 Access : R/W
    - 7:2 Reserved.
    TIMER_TRIG 1 set: Enable timer counting one time (from 0 to max, then stop).
    clear: By reset itself OR set reg_timer_en.
    TIMER_EN 0 set: Enable timer counting rolled (from 0 to max, then rolled).
    clear: By reset itself OR set reg_timer_trig.
    40h (3081h) REG3081 7:0 Default : 0x00 Access : R/W
    - 7:1 Reserved.
    TIMER_INT_EN 0 set: Enable interrupt.
    clear: By reset itself.
    41h (3082h) REG3082 7:0 Default : 0x00 Access : RO
    - 7:1 Reserved.
    TIMER_HIT 0 assert: When counter enabled and matches reg_timer_max.
    deassert: By write 1 OR set reg_timer_en, reg_timer_once, reg_timer_max.
    42h (3084h) REG3084 7:0 Default : 0xFF Access : R/W
    TIMER_MAX[7:0] 7:0 Timer maximum value.
    42h (3085h) REG3085 7:0 Default : 0xFF Access : R/W
    TIMER_MAX[15:8] 7:0 See description of '3084h'.
    43h (3086h) REG3086 7:0 Default : 0xFF Access : R/W
    TIMER_MAX[23:16] 7:0 See description of '3084h'.
    43h (3087h) REG3087 7:0 Default : 0xFF Access : R/W
    TIMER_MAX[31:24] 7:0 See description of '3084h'.
    44h (3088h) REG3088 7:0 Default : 0x00 Access : RO
    TIMER_CAP[7:0] 7:0 Timer current value.
    Note: With non-32-bit-data system, please read from LSB.
    44h (3089h) REG3089 7:0 Default : 0x00 Access : RO
    TIMER_CAP[15:8] 7:0 See description of '3088h'.
    45h (308Ah) REG308A 7:0 Default : 0x00 Access : RO
    TIMER_CAP[23:16] 7:0 See description of '3088h'.
    45h (308Bh) REG308B 7:0 Default : 0x00 Access : RO
    TIMER_CAP[31:24] 7:0 See description of '3088h'.
    46h (308Ch) REG308C 7:0 Default : 0x00
    TIMER_DIVIDE[7:0] 7:0 timer divide counter number
    8'b0000: timer counter = clk_xiu/1
    8'b0001: timer counter = clk_xiu/2
    8'b0010: timer counter = clk_xiu/3
    and so on

    2.5. TIMER4 Register (Bank = 30)

    Index (Absolute) Mnemonic Bit Description
    50h (30A0h) REG30A0 7:0 Default : 0x00 Access : R/W
    - 7:2 Reserved.
    TIMER_TRIG 1 set: Enable timer counting one time (from 0 to max, then stop).
    clear: By reset itself OR set reg_timer_en.
    TIMER_EN 0 set: Enable timer counting rolled (from 0 to max, then rolled).
    clear: By reset itself OR set reg_timer_trig.
    50h (30A1h) REG30A1 7:0 Default : 0x00 Access : R/W
    - 7:1 Reserved.
    TIMER_INT_EN 0 set: Enable interrupt.
    clear: By reset itself.
    51h (30A2h) REG30A2 7:0 Default : 0x00 Access : RO
    - 7:1 Reserved.
    TIMER_HIT 0 assert: When counter enabled and matches reg_timer_max.
    deassert: By write 1 OR set reg_timer_en, reg_timer_once, reg_timer_max.
    52h (30A4h) REG30A4 7:0 Default : 0xFF Access : R/W
    TIMER_MAX[7:0] 7:0 Timer maximum value.
    52h (30A5h) REG30A5 7:0 Default : 0xFF Access : R/W
    TIMER_MAX[15:8] 7:0 See description of '30A4h'.
    53h (30A6h) REG30A6 7:0 Default : 0xFF Access : R/W
    TIMER_MAX[23:16] 7:0 See description of '30A4h'.
    53h (30A7h) REG30A7 7:0 Default : 0xFF Access : R/W
    TIMER_MAX[31:24] 7:0 See description of '30A4h'.
    54h (30A8h) REG30A8 7:0 Default : 0x00 Access : RO
    TIMER_CAP[7:0] 7:0 Timer current value.
    Note: With non-32-bit-data system, please read from LSB.
    54h (30A9h) REG30A9 7:0 Default : 0x00 Access : RO
    TIMER_CAP[15:8] 7:0 See description of '30A8h'.
    55h (30AAh) REG30AA 7:0 Default : 0x00 Access : RO
    TIMER_CAP[23:16] 7:0 See description of '30A8h'.
    55h (30ABh) REG30AB 7:0 Default : 0x00 Access : RO
    TIMER_CAP[31:24] 7:0 See description of '30A8h'.
    56h (30ACh) REG30AC 7:0 Default : 0x00
    TIMER_DIVIDE[7:0] 7:0 timer divide counter number
    8'b0000: timer counter = clk_xiu/1
    8'b0001: timer counter = clk_xiu/2
    8'b0010: timer counter = clk_xiu/3
    and so on

    2.6. TIMER5 Register (Bank = 30)

    Index (Absolute) Mnemonic Bit Description
    60h (30C0h) REG30C0 7:0 Default : 0x00 Access : R/W
    - 7:2 Reserved.
    TIMER_TRIG 1 set: Enable timer counting one time (from 0 to max, then stop).
    clear: By reset itself OR set reg_timer_en.
    TIMER_EN 0 set: Enable timer counting rolled (from 0 to max, then rolled).
    clear: By reset itself OR set reg_timer_trig.
    60h (30C1h) REG30C1 7:0 Default : 0x00 Access : R/W
    - 7:1 Reserved.
    TIMER_INT_EN 0 set: Enable interrupt.
    clear: By reset itself.
    61h (30C2h) REG30C2 7:0 Default : 0x00 Access : RO
    - 7:1 Reserved.
    TIMER_HIT 0 assert: When counter enabled and matches reg_timer_max.
    deassert: By write 1 OR set reg_timer_en, reg_timer_once, reg_timer_max.
    62h (30C4h) REG30C4 7:0 Default : 0xFF Access : R/W
    TIMER_MAX[7:0] 7:0 Timer maximum value.
    62h (30C5h) REG30C5 7:0 Default : 0xFF Access : R/W
    TIMER_MAX[15:8] 7:0 See description of '30C4h'.
    63h (30C6h) REG30C6 7:0 Default : 0xFF Access : R/W
    TIMER_MAX[23:16] 7:0 See description of '30C4h'.
    63h (30C7h) REG30C7 7:0 Default : 0xFF Access : R/W
    TIMER_MAX[31:24] 7:0 See description of '30C4h'.
    64h (30C8h) REG30C8 7:0 Default : 0x00 Access : RO
    TIMER_CAP[7:0] 7:0 Timer current value.
    Note: With non-32-bit-data system, please read from LSB.
    64h (30C9h) REG30C9 7:0 Default : 0x00 Access : RO
    TIMER_CAP[15:8] 7:0 See description of '30C8h'.
    65h (30CAh) REG30CA 7:0 Default : 0x00 Access : RO
    TIMER_CAP[23:16] 7:0 See description of '30C8h'.
    65h (30CBh) REG30CB 7:0 Default : 0x00 Access : RO
    TIMER_CAP[31:24] 7:0 See description of '30C8h'.
    66h (30CCh) REG30CC 7:0 Default : 0x00
    TIMER_DIVIDE[7:0] 7:0 timer divide counter number
    8'b0000: timer counter = clk_xiu/1
    8'b0001: timer counter = clk_xiu/2
    8'b0010: timer counter = clk_xiu/3
    and so on