Timer使用参考
1. 使用说明¶
1.1. 启用Timer¶
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Enable Timer engine – set “TIMER_EN” to 1
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Trigger counter – set” TIMER_TRIG” to 1.
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Read timer from register “TIMER_CAP[31:0]”
1.2. 设定最大值¶
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Set the value to “TIMER_MAX[31:0]”.
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Enable timer
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If counter over the “TIMER_MAX[31:0]”, then “TIMER_HIT” will assert.
2. Timer寄存器表¶
2.1. TIMER0寄存器(Bank = 30)¶
Index (Absolute) | Mnemonic | Bit | Description | |
---|---|---|---|---|
(1840h) | REG1840 | 7:0 | Default : 0x00 | Access : R/W |
- | 7:2 | Reserved. | ||
TIMER_TRIG | 1 | set: Enable timer counting one time (from 0 to max, then stop). clear: By reset itself OR set reg_timer_en. |
||
TIMER_EN | 0 | set: Enable timer counting rolled (from 0 to max, then rolled). clear: By reset itself OR set reg_timer_trig. |
||
(1840h) | REG1840 | 7:0 | Default : 0x00 | Access : R/W |
- | 7:1 | Reserved. | ||
TIMER_INT_EN | 0 | set: Enable interrupt. clear: By reset itself. |
||
(1841h) | REG1841 | 7:0 | Default : 0x00 | Access : RO |
- | 7:1 | Reserved. | ||
TIMER_HIT | 0 | assert: When counter enabled and matches reg_timer_max. deassert: By write 1 OR set reg_timer_en, reg_timer_once, reg_timer_max. |
||
(1842h) | REG1842 | 7:0 | Default : 0xFF | Access : R/W |
TIMER_MAX[7:0] | 7:0 | Timer maximum value. | ||
(1842h) | REG1842 | 7:0 | Default : 0xFF | Access : R/W |
TIMER_MAX[15:8] | 7:0 | See description of '1842h'. | ||
(1843h) | REG1843 | 7:0 | Default : 0xFF | Access : R/W |
TIMER_MAX[23:16] | 7:0 | See description of '1842h'. | ||
(1843h) | REG1843 | 7:0 | Default : 0xFF | Access : R/W |
TIMER_MAX[31:24] | 7:0 | See description of '1842h'. | ||
(1844h) | REG1844 | 7:0 | Default : 0x00 | Access : RO |
TIMER_CAP[7:0] | 7:0 | Timer current value. Note: With non-32-bit-data system, please read from LSB. |
||
(1844h) | REG1844 | 7:0 | Default : 0x00 | Access : RO |
TIMER_CAP[15:8] | 7:0 | See description of '1844h'. | ||
(1845h) | REG1845 | 7:0 | Default : 0x00 | Access : RO |
TIMER_CAP[23:16] | 7:0 | See description of '1844h'. | ||
(1845h) | REG1845 | 7:0 | Default : 0x00 | Access : RO |
TIMER_CAP[31:24] | 7:0 | See description of '1844h'. |
2.2. TIMER1寄存器(Bank = 30)¶
Index (Absolute) | Mnemonic | Bit | Description | |
---|---|---|---|---|
(1820h) | REG1820 | 7:0 | Default : 0x00 | Access : R/W |
- | 7:2 | Reserved. | ||
TIMER_TRIG | 1 | set: Enable timer counting one time (from 0 to max, then stop). clear: By reset itself OR set reg_timer_en. |
||
TIMER_EN | 0 | set: Enable timer counting rolled (from 0 to max, then rolled). clear: By reset itself OR set reg_timer_trig. |
||
(1820h) | REG1820 | 7:0 | Default : 0x00 | Access : R/W |
- | 7:1 | Reserved. | ||
TIMER_INT_EN | 0 | set: Enable interrupt. clear: By reset itself. |
||
(1821h) | REG1821 | 7:0 | Default : 0x00 | Access : RO |
- | 7:1 | Reserved. | ||
TIMER_HIT | 0 | assert: When counter enabled and matches reg_timer_max. deassert: By write 1 OR set reg_timer_en, reg_timer_once, reg_timer_max. |
||
(1822h) | REG1822 | 7:0 | Default : 0xFF | Access : R/W |
TIMER_MAX[7:0] | 7:0 | Timer maximum value. | ||
(1822h) | REG1822 | 7:0 | Default : 0xFF | Access : R/W |
TIMER_MAX[15:8] | 7:0 | See description of '1822h'. | ||
(1823h) | REG1823 | 7:0 | Default : 0xFF | Access : R/W |
TIMER_MAX[23:16] | 7:0 | See description of '1823h'. | ||
(1823h) | REG1823 | 7:0 | Default : 0xFF | Access : R/W |
TIMER_MAX[31:24] | 7:0 | See description of '1823h'. | ||
(1824h) | REG1824 | 7:0 | Default : 0x00 | Access : RO |
TIMER_CAP[7:0] | 7:0 | Timer current value. Note: With non-32-bit-data system, please read from LSB. |
||
(1824h) | REG1824 | 7:0 | Default : 0x00 | Access : RO |
TIMER_CAP[15:8] | 7:0 | See description of '1824h'. | ||
(1825h) | REG1825 | 7:0 | Default : 0x00 | Access : RO |
TIMER_CAP[23:16] | 7:0 | See description of '1824h'. | ||
(1825h) | REG1825 | 7:0 | Default : 0x00 | Access : RO |
TIMER_CAP[31:24] | 7:0 | See description of '1824h'. |
2.3. TIMER2寄存器(Bank = 30)¶
Index (Absolute) | Mnemonic | Bit | Description | |
---|---|---|---|---|
(1810h) | REG1810 | 7:0 | Default : 0x00 | Access : R/W |
- | 7:2 | Reserved. | ||
TIMER_TRIG | 1 | set: Enable timer counting one time (from 0 to max, then stop). clear: By reset itself OR set reg_timer_en. |
||
TIMER_EN | 0 | set: Enable timer counting rolled (from 0 to max, then rolled). clear: By reset itself OR set reg_timer_trig. |
||
(1810h) | REG1810 | 7:0 | Default : 0x00 | Access : R/W |
- | 7:1 | Reserved. | ||
TIMER_INT_EN | 0 | set: Enable interrupt. clear: By reset itself. |
||
(1811h) | REG1811 | 7:0 | Default : 0x00 | Access : RO |
- | 7:1 | Reserved. | ||
TIMER_HIT | 0 | assert: When counter enabled and matches reg_timer_max. deassert: By write 1 OR set reg_timer_en, reg_timer_once, reg_timer_max. |
||
(1812h) | REG1812 | 7:0 | Default : 0xFF | Access : R/W |
TIMER_MAX[7:0] | 7:0 | Timer maximum value. | ||
(1812h) | REG1812 | 7:0 | Default : 0xFF | Access : R/W |
TIMER_MAX[15:8] | 7:0 | See description of '1812h'. | ||
(1813h) | REG1813 | 7:0 | Default : 0xFF | Access : R/W |
TIMER_MAX[23:16] | 7:0 | See description of '1812h'. | ||
(1813h) | REG1813 | 7:0 | Default : 0xFF | Access : R/W |
TIMER_MAX[31:24] | 7:0 | See description of '1812h'. | ||
(1814h) | REG1814 | 7:0 | Default : 0x00 | Access : RO |
TIMER_CAP[7:0] | 7:0 | Timer current value. Note: With non-32-bit-data system, please read from LSB. |
||
(1814h) | REG1814 | 7:0 | Default : 0x00 | Access : RO |
TIMER_CAP[15:8] | 7:0 | See description of '1814h'. | ||
(1815h) | REG1815 | 7:0 | Default : 0x00 | Access : RO |
TIMER_CAP[23:16] | 7:0 | See description of '1815h'. | ||
(1815Bh) | REG1815 | 7:0 | Default : 0x00 | Access : RO |
TIMER_CAP[31:24] | 7:0 | See description of '1815h'. |