Timer使用参考

version 1.0


1. 使用说明


1.1. 启用定时器

  1. 启用定时器 – “TIMER_EN” 置 1

  2. 触发计数器 – “TIMER_TRIG” 置 1.

  3. 从寄存器读定时器 - “TIMER_CAP[31:0]”

1.2. 设置分频和最大值

  1. 将定时器/计数器的频率的“ divide”值设置为“ TIMER_DIVIDE [7:0]”

  2. 将“max”值设置为“ TIMER_MAX [31:0]”

  3. 启用定时器

  4. 如果计数器超过“ TIMER_MAX [31:0]”, 则“ TIMER_HIT”将置位


2. 寄存器


2.1. TIMER0 寄存器 (Bank = 30)

表2-1

索引 (Absolute)符号Bit描述
10h (3020h)REG30207:0Default : 0x00Access : R/W
-7:2保留
TIMER_TRIG1set: Enable timer counting one time (from 0 to max, then stop).
clear: By reset itself OR set reg_timer_en.
TIMER_EN0set: Enable timer counting rolled (from 0 to max, then rolled).
clear: By reset itself OR set reg_timer_trig.
10h (3021h)REG30217:0Default : 0x00Access : R/W
-7:1保留
TIMER_INT_EN0set: Enable interrupt.
clear: By reset itself.
10h (3022h)REG30227:0Default : 0x00Access : RO
-7:1保留
TIMER_HIT0assert: When counter enabled and matches reg_timer_max.
deassert: By write 1 OR set reg_timer_en, reg_timer_once, reg_timer_max.
12h (3024h)REG30247:0Default : 0xFFAccess : R/W
TIMER_MAX[7:0]7:0Timer maximum value.
12h (3025h)REG30257:0Default : 0xFFAccess : R/W
TIMER_MAX[15:8]7:0See description of '3024h'.
13h (3026h)REG30267:0Default : 0xFFAccess : R/W
TIMER_MAX[23:16]7:0See description of '3024h'.
13h (3027h)REG30277:0Default : 0xFFAccess : R/W
TIMER_MAX[31:24]7:0See description of '3024h'.
14h (3028h)REG30287:0Default : 0x00Access : RO
TIMER_CAP[7:0]7:0Timer current value.
Note: With non-32-bit-data system, please read from LSB.
14h (3029h)REG30297:0Default : 0x00Access : RO
TIMER_CAP[15:8]7:0See description of '3028h'.
15h (302Ah)REG302A7:0Default : 0x00Access : RO
TIMER_CAP[23:16]7:0See description of '3028h'.
15h (302Bh)REG302B7:0Default : 0x00Access : RO
TIMER_CAP[31:24]7:0See description of '3028h'.
16h (302Ch)REG302C7:0Default : 0x00Access : R/W
TIMER_DIVIDE[7:0]7:0 timer divide counter number
8'b0000: timer counter = clk_xiu/1
8'b0001: timer counter = clk_xiu/2
8'b0010: timer counter = clk_xiu/3
and so on.

2.2. TIMER1 寄存器 (Bank = 30)

表2-2

索引 (Absolute)符号Bit描述
20h (3040h)REG30407:0Default : 0x00Access : R/W
-7:2保留
TIMER_TRIG1set: Enable timer counting one time (from 0 to max, then stop).
clear: By reset itself OR set reg_timer_en.
TIMER_EN0set: Enable timer counting rolled (from 0 to max, then rolled).
clear: By reset itself OR set reg_timer_trig.
20h (3041h)REG30417:0Default : 0x00Access : R/W
-7:1保留
TIMER_INT_EN0set: Enable interrupt.
clear: By reset itself.
21h (3042h)REG30427:0Default : 0x00Access : RO
-7:1保留
TIMER_HIT0assert: When counter enabled and matches reg_timer_max.
deassert: By write 1 OR set reg_timer_en, reg_timer_once, reg_timer_max.
22h (3044h)REG30447:0Default : 0xFFAccess : R/W
TIMER_MAX[7:0]7:0Timer maximum value.
22h (3045h)REG30457:0Default : 0xFFAccess : R/W
TIMER_MAX[15:8]7:0See description of '3044h'.
23h (3046h)REG30467:0Default : 0xFFAccess : R/W
TIMER_MAX[23:16]7:0See description of '3044h'.
23h (3047h)REG30477:0Default : 0xFFAccess : R/W
TIMER_MAX[31:24]7:0See description of '3044h'.
24h (3048h)REG30487:0Default : 0x00Access : RO
TIMER_CAP[7:0]7:0Timer current value.
Note: With non-32-bit-data system, please read from LSB.
24h (3049h)REG30497:0Default : 0x00Access : RO
TIMER_CAP[15:8]7:0See description of '3048h'.
25h (304Ah)REG304A7:0Default : 0x00Access : RO
TIMER_CAP[23:16]7:0See description of '3048h'.
25h (304Bh)REG304B7:0Default : 0x00Access : RO
TIMER_CAP[31:24]7:0See description of '3048h'.
26h (304Ch)REG304C7:0Default : 0x00Access : RO
TIMER_DIVIDE[7:0]7:0timer divide counter number
8'b0000: timer counter = clk_xiu/1
8'b0001: timer counter = clk_xiu/2
8'b0010: timer counter = clk_xiu/3
and so on

2.3. TIMER2 寄存器 (Bank = 30)

表2-3

索引 (Absolute)符号Bit描述
30h (3060h)REG30607:0Default : 0x00Access : R/W
-7:2保留
TIMER_TRIG1set: Enable timer counting one time (from 0 to max, then stop).
clear: By reset itself OR set reg_timer_en.
TIMER_EN0 set: Enable timer counting rolled (from 0 to max, then rolled).
clear: By reset itself OR set reg_timer_trig.
30h (3061h)REG30617:0Default : 0x00Access : R/W
-7:1保留
TIMER_INT_EN0set: Enable interrupt.
clear: By reset itself.
31h (3062h)REG30627:0Default : 0x00Access : RO
-7:1保留
TIMER_HIT0assert: When counter enabled and matches reg_timer_max.
deassert: By write 1 OR set reg_timer_en, reg_timer_once, reg_timer_max.
32h (3064h)REG30647:0Default : 0xFFAccess : R/W
TIMER_MAX[7:0]7:0Timer maximum value.
32h (3065h)REG30657:0Default : 0xFFAccess : R/W
TIMER_MAX[15:8]7:0See description of '3064h'.
33h (3066h)REG30667:0Default : 0xFFAccess : R/W
TIMER_MAX[23:16]7:0See description of '3064h'.
33h (3067h)REG30677:0Default : 0xFFAccess : R/W
TIMER_MAX[31:24]7:0See description of '3064h'.
34h (3068h)REG30687:0Default : 0x00Access : RO
TIMER_CAP[7:0]7:0Timer current value.
Note: With non-32-bit-data system, please read from LSB.
34h (3069h)REG30697:0Default : 0x00Access : RO
TIMER_CAP[15:8]7:0See description of '3068h'.
35h (306Ah)REG306A7:0Default : 0x00Access : RO
TIMER_CAP[23:16]7:0See description of '3068h'.
35h (306Bh)REG306B7:0Default : 0x00Access : RO
TIMER_CAP[31:24]7:0See description of '3068h'.
36h (306Ch)REG306C7:0Default : 0x00
TIMER_DIVIDE[7:0]7:0timer divide counter number
8'b0000: timer counter = clk_xiu/1
8'b0001: timer counter = clk_xiu/2
8'b0010: timer counter = clk_xiu/3
and so on